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and2.v |
and2testbench.v |
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module gate01(a,b,c); input a,b; output c; assign c=a&b; endmodule |
`timescale 1ns/1ns module testbench; reg x,y; wire z; gate01 g01(x,y,z); initial begin $dumpfile("tmp.vcd"); $dumpvars(); $monitor("%t %b %b %b",$time,x,y,z); x=1'b0; y=1'b0; #100 y=1'b1; #100 x=1'b1; y=1'b0; #100 y=1'b1; #100 x=1'b0; y=1'b0; #100 $finish; end endmodule |