module TestBench;
reg a1,a2;
reg b1,b2;
initial begin
$dumpfile("tmp.vcd");
$dumpvars(0,TestBench);
$display("a1 b1 | a2 b2");
$monitor(" %b %b | %b %b",a1,b1,a2,b2);
#0 a1=1'b0; b1=1'b1; a2=1'b0; b2=1'b1;
#1 a1=b1; b1=a1; a2<=b2; b2<=a2;
#1 a1=b1; b1=a1; a2<=b2; b2<=a2;
#1 a1=1'b0; b1=1'b0; a2=1'b0; b2=1'b0;
#1 a1=1'b1; b1=1'b0; a2=1'b1; b2=1'b0;
#1 a1=b1; b1=a1; a2<=b2; b2<=a2;
#1 a1=b1; b1=a1; a2<=b2; b2<=a2;
#1 $finish;
end
endmodule