task execute;
begin
nextState <= WriteBack;
case(ir[23:20])
`ADD, `ADC,
`SUB, `SUC,
`AND, `OR , `XOR, `NOT ,
`LD
: begin acc <= aluout; flag <= cz; end
`FIN : finishAction; /*シミュレーション終了処理*/
endcase
end
endtask
aluoutとフラグ(cz)をコピー
宣言が必要
reg […] acc;
reg […] flag;
wire […] ix,iy;
wire […] cz;